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Document Number: 69062
S10-1367-Rev. D, 14-Jun-10
Vishay Siliconix
SiC417
PIN CONFIGURATION
FB
FBL
V5V
A
GND
V
OUT
V
IN
V
LDO
BST
LX
LX
P
GND
P
GND
P
GND
P
GND
P
GND
P
GND
PAD 1
A
GND
 34
PAD 2
V
IN
 35
PAD 3
LX 33
PIN DESCRIPTION
Pin Number   Symbol
Description
1
FB
Feedback input for switching regulator. Connect to an external resistor divider from output to program the
output voltage.
2
FBL   Feedback input for the LDO. Connect to an external resistor divider from V
LDO
 to program the V
LDO
 output.
3
V5V
5 V power input for internal analog circuits and gate drives. Connect to external 5 V supply or configure the
LDO for 5 V and connect to V
LDO
.
4, 30, PAD 1    A
GND
Analog ground.
5
V
OUT
Output voltage input to the SiC417. Additionally, may be used to bypass LDO to supply V
LDO
directly.
6, 9 - 11, PAD 2    V
IN
Input supply voltage.
7
V
LDO
LDO output.
8
BST
Bootstrap pin. A capacitor is connected between BST to LX to develop the floating voltage for the high-side
gate drive.
12
DH   High-side gate drive - do not connect this pin.
14
DL    Low-side gate drive - do not connect this pin.
13, 23 - 25, 28,
PAD 3
LX    Switching (Phase) node.
15-22
P
GND
Power ground.
26
P
GOOD
Open-drain power good indicator. High impedance indicates power is good. An external pull-up resistor is
required.
27
I
LIM
Current limit sense point - to program the current limit connect a resistor from I
LIM
 to LX.
29
EN/PSV
Tri-state pin. Enable input for switching regulator. Connect EN to A
GND
 to disable the switching regulator.
Float pin for forced continuous and pull high for power-save mode.
31
t
ON
On-time set input. Set the on-time by a series resistor to the input supply voltage.
32
ENL   Enable input for the LDO. Connect ENL to A
GND
 to disable the LDO.
ORDERING INFORMATION
Part Number
Package
SiC417CD-T1-E3
MLPQ55-32
SiC417DB
Evaluation board
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